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Features
* Very Low-cost Configuration Memory * Programmable 1,048,576 x 1, 2,097,152 x 1, 4,194,304 x 1 and 7,340,032 x 1-bit Serial
Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) 1.8V, 2.5V, and 3.3V I/O 3.3V Supply Voltage Program Support using an Atmel Programmer or Industry-standard Third Party Programmers In-System Programmable (ISP) via JTAG Interface (IEEE 1532) IEEE 1149.1 Boundary-scan Testability Simple Interface to SRAM FPGAs Pin Compatible with Xilinx(R) XCFxxS Series Platform Flash PROM to Configure Xilinx Spartan(R) and Virtex(R) FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density FPGAs Low-power CMOS FLASH Process Available in 20-lead TSSOP Package Low-power Standby Mode Fast Serial Download Speeds up to 33 MHz Endurance: 100,000 Write Cycles Typical Green (Pb/Halide-free/RoHS Compliant) Package Functionally-compatible with Existing AT17 Series Configuration Memories to Configure Atmel AT40KAL Series FPGAs
* * * * * * * * * * * * * * *
FPGA Configuration Flash Memory AT18F010 AT18F002 AT18F040 AT18F080 Preliminary
AT18F Series Configuration Memory Offering
AT18F010 Density JTAG Programming VCCINT VCCO VCCJ Configuration Clock Package Green Package 1 Mbit AT18F002 2 Mbit Yes 3.3V 1.8-3.3V 1.8-3.3V 33 MHz 20-lead TSSOP Yes AT18F040 4 Mbit AT18F080 7 Mbit
1. Description
The AT18F Series of JTAG In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT18F Series device is packaged in a 20-lead TSSOP. The AT18F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT18F Series Configurators can be programmed with Atmel or industry-standard, third-party, stand-alone programmers such as BP, Data I/O, Hi-Lo, etc.
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2. Pin Configuration
20-lead TSSOP
DATA NC CLK TDI TMS TCK CF RESET/OE NC CE
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCCJ VCCO VCCINT TDO NC NC NC CEO NC GND
3. Block Diagram
Power-on Reset JTAG Interface
TCK TMS TDI TDO
Internal Oscillator Controller CF
CE Download Interface Flash Memory RESET/OE CEO DATA
CLK
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
4. Device Description
The download interface of the configuration memory will directly communicate with the FPGA through the interface-control signals (CLK, RESET/OE, CE) to initialize and terminate configuration. All FPGA devices in the master serial mode can control the entire configuration process to receive data from the configuration device without requiring an external intelligent controller. When FPGA devices are used in slave serial mode, an external clock signal can be applied to the CLK pin of an AT18F series device as a configuration loading clock. Multiple FPGAs that are setup in Master Serial and Slave Serial modes can also be used to control the configuration process to obtain data from a single configurator or cascaded configurators. Please contact Atmel at configurator@atmel.com for detailed descriptions. The CF pin is used as an optional input pin for the JTAG CONFIG instruction to initialize the FPGA configuration without requiring powering down the device. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT18F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is reset and the DATA output pin is tri-stated. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
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AT18F series devices are compatible with a portion of the Xilinx's FGPA device families. Table 4-1.
Atmel Virtex-II XC2V80 Virtex-II XCV50E Virtex-E XCV100E XCV50 Virtex XCV100 XCV150 AT18F040-30XU Spartan-3E AT18F010-30XU Spartan-3 XC3S200 XC2S50E Spartan-IIE XC2S100E XC2S15 Spartan-IIE XC2S30 Spartan-II XC2S50 XC2S100 Virtex-4 LX XC2S150 Virtex-II Pro Virtex-II Virtex-E XCV300E Virtex-II Pro XCV200 Virtex XCV300 AT18F002-30XU Spartan-3E Spartan-3 XC3S250E XC3S400 XC2S150E Spartan-IIE XC2S200E XC2S300E Virtex Spartan-II XC2S200 Spartan-3E Spartan-3L Spartan-3 XC3S2000 XCV1000 XC3S1600E XC3S1500L XC3S1500 Virtex-E AT18F080-30XU Virtex-II XC2V2000 XCV812E XCV1000E XCV1600E XCV800 XC2V1500 XC2VP20 XC2VP7 XC2VP2 Virtex-4 FX XC2V250 XCV200E Virtex-II Pro X XC4VFX20 XC2VPX20 XC4VLX25 XC4VFX12 Virtex-5 LX XC2S600E XC5VLX30 XC4VLX15 Spartan-3 XC3S1000 XC2S400E Spartan-3L XC3S100E XC3S50 Spartan-3E XC3S1200E XC3S1000L Virtex XCV600 XC3S500E Virtex-E XCV400E XCV405E XCV600E XCV400 XC2V1000 XC2V500
AT18F Series Configurator Compatibility with Xilinx FPGAs
Xilinx XC2V40 Atmel Virtex-II Pro Xilinx XC2VP4
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
5. Programming
AT18Fxx devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the AT18Fxx via the PC. ISP is performed by using either a download cable or a comparable board tester or a simple microprocessor interface. To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by the Atmel JCPS Software. Conversion to other ATE tester format beside SVF is also possible AT18Fxx devices can also be programmed using standard third-party programmers such as BP, DataI/O, Hi-Lo, etc. Factory-preprogrammed devices, as required by customers, are also available for certain ordering quantities. Contact your local Atmel representatives or Atmel PLD applications for details.
5.1
JTAG-BST Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the AT18F series. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The AT18Fxx series does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The six JTAG BST modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the AT18Fxx series is implemented using the Boundary-scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used to perform BST on the AT18Fxx series. The AT18F series uses the four JTAG-standard I/O pins for In-System programming (ISP). The AT18F series is programmable through the four JTAG pins using programming algorithm compatible with the IEEE JTAG Standard 1532. Programming is performed by using selectable voltage levels of the programming signals from the JTAG ISP interface.
5.2
JTAG Boundary-scan Cell (BSC) Testing
The AT18F series has I/Os that contain boundary-scan cells (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller.
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6. Pin Description
Table 6-1.
Name DATA CLK RESET/OE CE CF CEO TMS TCK TDI TDO VCCINT NC VCCO GND VCCJ
Pin Descriptions
Type I/O I I I I O I I I O I Power Supply Ground Power Supply 20-lead TSSOP 1 3 8 10 7 13
5
6 4 17 18 2, 9, 12, 14, 15, 16 19 11 20
6.1
DATA (D0)
Open-collector bi-directional data pin. This pin has an internal 20 K pull-up resistor.
6.2
CLK
Clock input. Used to increment the internal address and bit counter for reading and programming. This pin has an internal 20 K pull-up resistor.
6.3
RESET/OE
Output Enable (active High) and RESET (active Low). A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. This pin has an internal 20 K pull-up resistor.
6.4
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. This pin has an internal 20 K pull-up resistor.
6.5
CF
Configuration Pulse (open-drain output). Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down the FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command.
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
6.6 CEO
Chip Enable Output for configuration download. This output goes Low when the internal address counter of the device has reached its maximum value which signals that all configuration data is being clocked out of the device. In a daisy chain of AT18F Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire memory device is read again.
6.7
TMS
JTAG Mode Control Input. The state of TMS with the rising edge of TCK determines the state transitions of the Test Access Port (TAP) controller. TMS has an internal 50 K weak pull-up to VCCJ to provide a logic 1 to the device.
6.8
TCK
JTAG Clock Input. This pin is the JTAG clock input to the TAP controller of the device.
6.9
TDI
JTAG Serial Data Input. This pin is the serial input to all JTAG instructions and data registers. An internal 50 K weak pull-up to VCCJ provides a logic 1 to the device.
6.10
TDO
JTAG Serial Data Output. This pin is the serial output to all JTAG instruction and data registers. An internal 50 K weak pull-up to VCCJ provides a logic 1 to the device if the pin is not driven.
6.11
VCCINT
+3.3V supply voltage for internal logic.
6.12
NC
No Connect Pin. This pin is not connected to any internal logic of the device and can be left floating.
6.13
VCCO
Supply voltage for I/O drivers (1.8V, 3.3V, or 3.3V).
6.14
VCCJ
Supply voltage for JTAG I/O drivers (1.8V, 3.3V, or 3.3V).
6.15
GND
Power supply ground.
7. Standby Mode
The AT18F Series Configurators enter a low-power standby mode whenever the JTAG mode is inactive and CE is asserted High. In this mode, the AT18F Configurator consumes less than 1 mA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input.
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8. Configuration Memory to FPGA Device Interface Connection Diagrams
Figure 8-1. General Connection Diagram for Loading FPGA from Configurator and JTAG Signals
Notes:
1. Signals within parenthesis will be applied to Atmel AT40AK FPGA. 2. For details of the circuit connection, please contact factory.
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
9. Absolute Maximum Ratings*
Operating Temperature................................. -55 C to +125 C Storage Temperature .................................... -65 C to +150 C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +3.6V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260 C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
10. Operating Conditions
TAI = -40 C to +85 C for Industrial and 0 C to +70 C for Commercial
Symbol VCCINT Description Supply Voltage for Internal Logic 3.3V Operation VCCO Supply Voltage for I/O Drivers 2.5V Operation 1.8V Operation 3.3V Operation Min 3.0 3.0 2.3 1.7 3.0 2.3 1.7 -0.3 -0.3 -0.3 2.0 1.7 0.65 x VCCO Typ 3.3 3.3 2.5 1.8 3.3 2.5 1.8 Max 3.6 3.6 2.7 1.9 3.6 2.7 1.9 0.8 0.7 0.35 x VCCO 3.9 3.9 3.9 V V V V Units V
VCCJ
Supply Voltage for JTAG I/O Drivers
2.5V Operation 1.8V Operation 3.3V Operation
VIL
Input Low Voltage
2.5V Operation 1.8V Operation 3.3V Operation
VIH
Input High Voltage
2.5V Operation 1.8V Operation
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11. DC Characteristics
Symbol ICCINT ICCIO ICCJ ICCINTS ICCIOS ICCJS IIL IIH Description Internal Voltage Supply Current, Active Mode I/O Drive Supply Current, Active Mode JTAG Supply Current, Active Mode Internal Voltage Supply Current, Standby Mode Output Drive Supply Current, Standby Mode JTAG Supply Current, Standby Mode Input or I/O Low Leakage Input or I/O High Leakage 3.3V Operation VOL Output Low Voltage 2.5V Operation 1.8V Operation 3.3V Operation VOH Output High Voltage 2.5V Operation 1.8V Operation VCCO - 0.4 VCCO - 0.4 VCCO - 0.45 V -10 VCCINT = 3.6V, VCIO = 3.6V VCCINT = 3.6V, VCIO = 3.6V VCCINT = 3.6V, VCIO = 3.6V 1 10 Condition 33 MHz 33 MHz Min Typ Max 10 10 5 1 1 1 10 10 0.4 0.4 0.45 V Units mA mA mA mA mA mA A A
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
12. AC Characteristics
Figure 12-1. AT18Fxx as Configuration Slave with CLK Input Pin as Clock Source
CE TSCE RESET/OE TCYC THC CLK TOE TCE DATA TCF CF TOH TCAC TOH TDF TLC THCE THOE
Table 12-1.
Symbol TCF TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE TBLKE
AC Characteristics over Operating Conditions
Description CF to Data Delay RESET/OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, RESET/OE, CLK, or CF CE or RESET/OE to Data Float Delay Clock Period CLK Low Time CLK High Time CE Setup Time to CLK CE Hold Time RESET/OE Hold Time Block Erase Time Bulk Erase Time - 1M Bulk Erase Time - 2M 30 15 15 20 250 250 0.7 1 3 5 9 15 100 20 15 15 25 Min 20 Max 50 10 Units s ns s ns ns ns ns ns ns s ns ns s s s s s ns
TERASE
Bulk Erase Time - 4M Bulk Erase Time - 8M
TCK_J
TAP Clock Minimum Period
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Figure 12-2. AC Characteristics when Cascading
RESET/OE
CE
CLK TCDF DATA LAST BIT TOCK CEO TOCE TOOE FIRST BIT
Table 12-2.
Symbol TCDF TOCK TOCE TOOE
AC Characteristics When Cascading
Description CLK to Output Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Min Max 25 20 20 20 Units ns ns ns ns
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
13. Ordering Information
Memory Size 1-Mbit 2-Mbit 4-Mbit 7-Mbit Ordering Code AT18F010-30XU AT18F002-30XU AT18F040-30XU AT18F080-30XU Package 20A2 - 20 TSSOP 20A2 - 20 TSSOP 20A2 - 20 TSSOP 20A2 - 20 TSSOP Operation Range Industrial (-40 C to 85 C) Industrial (-40 C to 85 C) Industrial (-40 C to 85 C) Industrial (-40 C to 85 C)
Package Type 20A2 20-lead, 0.65 mm Wide, Plastic Think-Shrink Small Outline (TSSOP)
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14. Packaging Information
14.1 20A2 - TSSOP
b L
Marked Pin1 Indentifier
E
E E1
L1
D
A A1
Top View
e
0.10 mm TYP
Side View
L1
Pin1 Corner
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 2, 5
8
Top View
D
1
e
A
7 2
D
A2
E E1 SYMBOL AA A2 A1 bb eD LE L1 e
6.40 6.60 COMMON6.50 DIMENSIONS (Unit of Measure = mm) 6.40 BSC 4.30 MIN - 0.94 0.80 0.30 0.19 0.45 5.89 0.45 4.89 4.40 NOM - 1.04 1.00 0.34 - 0.50 0.65 BSC 5.99 0.60 5.99 1.00 REF 1.27 BSC 4.50 MAX 1.20 1.14 1.05 0.38 0.30 0.55 6.09 0.75 6.09
3, 5 NOTE
6
3
b
5 4
4 1
Side View
e1
Notes:
L
e1 1.10 REF 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional information. L 0.95 1.00 1.05 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall L1 1.25 1.30 1.35 not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 Metal Pad Dimensions. Note: 1.mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H.
Bottom View
1 1
6/3/02 11/14/01 2325 Orchard Parkway 2325 Orchard Parkway San Jose, CA 95131 San Jose, CA 95131 TITLE TITLE 20A2, 20-lead x 6 x 6.5 mm Body), Lead Pitch 8CN4, 8-lead (6 (4.4 x 1.04mm Body), 0.65 pitch, 1.27 mm, Thin Shrink Small Outline Package (TSSOP) Leadless Array Package (LAP) DRAWING NO. 8CN4 20A2 REV. A C
R R
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AT18F010/002/040/080 [Preliminary]
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AT18F010/002/040/080 [Preliminary]
15. Revision History
Revision Level - Release Date A - January 2008 History Initial release.
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support configurator@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
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